Synchronous memory
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United States of America Patent
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Jun 19, 2001
Grant Date -
N/A
app pub date -
Feb 4, 2000
filing date -
Feb 6, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A synchronous single port random access memory comprises a core 2 of memory cells 3 arranged as rows and columns. The rows are addressed by a row decoder 5 and the memory cell outputs are connected as columns to a column decoder and multiplexer 7. The decoder and multiplexer 7 selects groups of memory cells 3 from the addressed row and connects these to sense amplifiers 8. Changes in address are propagated immediately to the core 2 so that the selected memory cells 3 are connected as quickly as possible and without any fixed delays to the sense amplifiers 8. Similarly, a read clock 'rclk' enables the sense amplifiers 8 immediately upon becoming active.
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