Logic circuits
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United States of America Patent
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Jun 19, 2001
Grant Date -
N/A
app pub date -
May 18, 1998
filing date -
Nov 16, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A transparent latch, having a signal input D, an output Q and a control input C for selecting one of two operating modes, functions by either allowing the output to follow the input (in an enable mode) or by blocking any subsequent changes in input signal level (in an inhibit mode). Owing to the design of the latch, relative propagation delays through gates and interconnecting wires cannot cause a wrong value to be latched, this being in contrast with known arrangements. Therefore constraints on the physical layout of the latch are removed. In one embodiment the latch comprises two pairs of NAND gates (5,6,7,8) each pair being connected in a feedback configuration.
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