Programmable hit and write policy for cache memory test
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United States of America Patent
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May 29, 2001
Grant Date -
N/A
app pub date -
Apr 6, 1998
filing date -
Apr 6, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a program test of the cache of a microprocessor, a forced hit signal can be set by the CPU. The forced hit signal allows for a more complete testing of the cache. Additionally, a forced write back signal can also be produced. In one embodiment, the forced hit signal will cause the tag RAM to be updated during a write with the forced hit.
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