Facility to allow fast execution of and, or, and test instructions
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 15, 2001
Grant Date -
N/A
app pub date -
Mar 25, 1999
filing date -
Mar 25, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Improvements are made in how microprocessors execute AND, OR, and TEST instructions when the operands of this instruction are equal. AND/OR/TEST instructions with equal operands are used to set flags based on the contents of the single operand without explicitly performing the actual AND/OR/TEST command. By resetting these flags directly, this mechanism allows these instructions to be paired with preceding dependent instructions simply by using the flags set by the AND/OR/TEST for the previous instruction. An architecture that hardwires the implementation into the microprocessor through logic gates is preferred. This will result in increased speed while reducing power consumption. Further, a full-sized ALU is not needed in order to execute the AND/OR/TEST instruction with equal operands. As this is a more direct procedure, a pipeline with a reduced capability ALU can be utilized.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully