Class D modulator with peak current limit and load impedance sensing circuits
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United States of America Patent
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May 8, 2001
Grant Date -
N/A
app pub date -
Nov 12, 1999
filing date -
Nov 18, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The OCL 200 receives two logic signals: the first, OC upper FET, is high when an over current condition exists in the upper FET 22; the second, OC lower FET, is high when an over current condition exists in the lower FET 24. When the over current condition is in FET 22, PMOS 212 turns on and injects current into the summing junction of the integrator 10 through Rcl. The net effect is turn off the upper FET 22 and turn on the lower FET 24. This reduces the current in FET 22. As far as amplifier 100 is concerned, the net effect is gain compression. Since upper FET 22 is on less and the lower FET 24 is on more, the gain of the audio signal is reduced. When the over current condition is in FET 24, NMOS 213 turns on and pulls current out of the summing junction, turns the lower FET 24 off, and turns the upper FET 22 on. The net effect is to reduce the current in the lower FET. At audio frequencies, the gain is reduced.
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