Importance

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Abstract

A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory. This eliminates the occurrence of penalty delay cycles that reduce the rate at which instructions are issued in existing processors, and thus improves the speed of operation of the processors.

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First Claim