Biasing scheme for GAASFET amplifier
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United States of America Patent
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Apr 17, 2001
Grant Date -
N/A
app pub date -
May 24, 1999
filing date -
May 26, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit.
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