Programmable logic device architecture with super-regions having logic regions and a memory region
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United States of America Patent
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Apr 10, 2001
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N/A
app pub date -
Mar 10, 1999
filing date -
Nov 18, 1998
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Abstract
A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
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