Combined Instruction and address caching system using independent buses
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United States of America Patent
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Mar 20, 2001
Grant Date -
N/A
app pub date -
Aug 27, 1993
filing date -
Jul 5, 1989
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Abstract
A microprocessor and a data processor therefor which have separate data and instruction buses, and wherein a data address and an instruction address are output over a single address bus in a time-shared manner, thereby allowing a data access and an instruction access to be pipelined without the need for separate address buses between the microprocessor and caches holding data and instructions.
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