Method of making electrical connections to integrated circuit
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United States of America Patent
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-
Mar 20, 2001
Grant Date -
N/A
app pub date -
Apr 29, 1998
filing date -
Aug 21, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a method of making electrical connections to an integrated chip, an oxide layer is formed on the surface of the chip and a substrate carrying electrical connections. The conductors on the chip are accurately aligned with the conductors on the substrate. An oxide layer formed on the surface of the chip is then fusion bonded to an oxide layer on the substrate and voids remaining between the conductors filled with a conductive material. This method removes the limitation imposed by the large pad size needed for conventional techniques.
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