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Abstract

A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback signal (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal (.phi..sub.CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal (.phi..sub.CH) and the error feedback signal (18) is produced by the second adder (16). The error signal (16A) is delayed a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal (.phi..sub.CH) is spread over a broad frequency spectrum between DC and F.sub.S /2. A pair of out-of-phase, non-overlapping chopping signals from the quantization signal (.phi..sub.CH). The chopping signals are applied to corresponding chopper switches of the chopper stabilized amplifier. The chopper stabilized amplifier is used in an integrator of a delta-sigma modulator to reduce sensitivity of analog-to-digital conversion to intermodulation in the delta-sigma modulator.

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