Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array
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United States of America Patent
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Feb 13, 2001
Grant Date -
N/A
app pub date -
Feb 12, 1999
filing date -
Jun 2, 1997
priority date (Note) -
Expired
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Abstract
An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.
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