Data processor capable of executing two instructions having operand interference at high speed in parallel
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United States of America Patent
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Jan 23, 2001
Grant Date -
N/A
app pub date -
Nov 9, 1995
filing date -
Nov 9, 1994
priority date (Note) -
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Abstract
A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.
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