Power-electronic circuit arrangement for compensating for mains system disturbances and mains voltage reductions
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United States of America Patent
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Jan 23, 2001
Grant Date -
N/A
app pub date -
Apr 2, 1999
filing date -
Apr 2, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a power-electronic circuit arrangement for compensating for mains system voltage reductions and mains system disturbances, a second auxiliary voltage source is provided, whose voltage is chosen to be less than that of the first auxiliary voltage source. The second auxiliary voltage source can be coupled to the feeder converter with the aid of a switch. The circuit according to the invention can thus operate in two different modes: when the first auxiliary voltage source is coupled to the feeder converter, the available voltage is sufficiently high to compensate for mains system failures or mains system voltage reductions. However, when less severe disturbances occur, the second, lower auxiliary voltage source is coupled to the feeder converter, and mains system disturbances can in consequence be compensated for without any major switching losses. The circuit then operates in a regulated mode, and the switching losses of the semiconductor switches in the feeder converter can be kept at an acceptable level, which is typically less than the losses when switched on. A further option for influencing the voltage is achieved by pulsing, in particular by pulse-width modulation of the switches, in a regulated mode.
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