Method of manufacturing vertical trench misfet
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United States of America Patent
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Jan 16, 2001
Issued Date -
N/A
app pub date -
Aug 27, 1999
filing date -
Feb 17, 1995
priority date (Note) -
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Abstract
A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage. A gate electrode is formed on an exposed surface of the second conductivity type base region, through a gate insulating film. A source electrode is disposed in contact with surfaces of both of the first conductivity type source region and the second conductivity type base region, while a drain electrode is disposed in contact with a rear surface of the first conductivity type semiconductor.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FUJI ELECTRIC CO LTD | KAWASAKI COUNTY OF KANAGAWA CITY JAPAN KAWASAKI-SHI KANAGAWA |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Fujishima, Naoto | Nagano, JP | 55 | 1150 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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