Process for fabrication of semiconductor device, semiconductor wafer for use in the process and process for the preparation of the wafer
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United States of America Patent
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-
Jan 16, 2001
Grant Date -
N/A
app pub date -
May 28, 1996
filing date -
Jun 9, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a process for the fabrication of a semiconductor integrated circuit using a double-side mirror-polished wafer or the like, at the portion of a notch 10 of a notched wafer 1, a chamfered angle .theta..sub.11 of the first chamfered portion 11 formed at the inner periphery of the first primary surface 3 is set smaller than the chamfered angle .theta..sub.12 of the second notch chamfered portion 12 of the second primary surface 4 and the chamfered width L.sub.11 is set larger than the chamfered width L.sub.12, whereby the obverse and reverse of the wafer are discriminated by optically discriminating the first notch chamfered portion and the second notch chamfered portion using reflected light, thereby making it certain to fabricate IC on the surface of the wafer and to use the reverse for its handling. The plane view of the notch in the circumferential direction can be maintained symmetrical so that the lowering in the symmetry of the wafer and the number of the IC available from the wafer can be prevented and the standards of the notch can be maintained.
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