Importance

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Abstract

Input partitioning logic is coupled to bit-lines of a content addressable memory (CAM) array having four-transistor (4-T) non-volatile Flash CAM cells. Prior to a program or search operation on the 4-T Flash CAM cells, two input data bits and their complements are applied to the input partitioning logic, which can be two-input NAND, NOR, AND, or OR gates. By selecting the appropriate values for the input bits, individual ones of the memory cells in the 4-T CAM cell can be programmed, or a desired two-bit pattern can be searched. The use of input partitioning logic prior to applying the search and program voltages to the bit-lines of the CAM cell results in substantially less voltage transitions during searches and less required programming current because fewer Flash memory cells are required to be programmed. Consequently, power consumption while operating the CAM array is substantially reduced, and the Flash memory cell endurance is effectively increased. Global masking techniques can be effectively applied to the input partitioning logic. These same techniques can also be used for DRAM-based CAM cells.

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