Integrated circuit for handling buffer contention and method thereof
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United States of America Patent
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Nov 14, 2000
Grant Date -
N/A
app pub date -
Jul 13, 1998
filing date -
Jul 13, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).
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