Hitless clock recovery in ATM networks
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United States of America Patent
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Nov 7, 2000
Grant Date -
N/A
app pub date -
Aug 25, 1997
filing date -
Aug 23, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of generating timing signals for constant bit rate data received over an asynchronous data network carrying, comprises recovering clock signals from at least two separate sources, selecting one of the sources to drive a phase-locked loop generating a high speed output signal locked to the selected source, dividing the high speed output signal to provide the required timing signals for said constant bit rate data, and continually monitoring the selected source. In the event of failure of the selected source, the phase-locked loop is allowed to free run in a hold-over mode while it is switched over to the other source.
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