Computational method and apparatus for finite field multiplication
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United States of America Patent
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Oct 24, 2000
Grant Date -
N/A
app pub date -
Sep 21, 1998
filing date -
Sep 22, 1997
priority date (Note) -
Expired
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Abstract
A method and a circuit for multiplication on a finite field which operate fast and involve a small circuit scale. There is provided a multiplication circuit on a finite field for multiplication of two arbitrary elements a=(a.sub.0, a.sub.1, . . . , a.sub.m-1) and b=(b.sub.0, b.sub.1, . . . , b.sub.m-1) of a Galois field GF(2.sup.m) utilizing a polynomial .function.=x.sup.m +x.sup.m-1 + . . . +x+1 as a polynomial to derive the GF(2.sup.m) where said f has an irreducible increased number of order, the multiplication circuit comprising a first shift register having m stages whose initial value is one of the elements of the Galois field, m AND gates to which the other element of the Galois field and an output signal from the last m-th stage of the first shift register are input, a second shift register having m+1 stages having an exclusive OR gate at the input of each of the first through m-th stages thereof, and second m exclusive OR gates to which an output signal from the last (m+1)-th stage of the second shift register and an output signal from the first through m-th stages are applied.
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