Method for planarized interconnect vias using electroless plating and CMP
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United States of America Patent
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Oct 24, 2000
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N/A
app pub date -
Oct 27, 1997
filing date -
Oct 27, 1997
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Abstract
An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
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