Three dimensional packaging configuration for multi-chip module assembly
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Oct 17, 2000
Grant Date -
N/A
app pub date -
Sep 24, 1998
filing date -
Oct 10, 1997
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A multi-chip module (MCM) assembly has three stacked integrated circuit (IC) layers. The first IC layer is electrically flip-chip connected to a substrate. The back of the second IC layer may be glued to the back of the first IC layer, and the second and third IC layers are electrically flip-chip connected to each other. In one embodiment, the third IC layer is electrically connected to the substrate through a vertical interconnect element for high circuit density. In another, the second IC layer is electrically connected to the substrate using wire bonding for greater post-fabrication customization flexibility. In still another embodiment, the MCM assembly comprises two stacked IC layers where the second IC layer is electrically flip-chip connected to the first IC layer and the second layer is electrically connected to the substrate through a vertical interconnect element. By directly connecting IC layers, higher circuit density, lower trace impedance, and lower cross-talk or electrical noise susceptibility is achieved over that presently offered by most current MCM assemblies. The assembly accommodates different sized IC layers, multiple ICs on each layer, and different technology-based IC layers and ICs within each layer, providing the user with high design flexibility within a single multi-chip assembly.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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SEMICONDUCTOR COMPONENTS INDUSTRIES LLC | 5005 E MCDOWELL ROAD MD A700 PHOENIX AS 85008 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Binapal, Sukhminder S | Burlington, CA | 3 | 182 |
# of filed Patents : 3 Total Citations : 182 | |||
Divita, Charles | Burlington, CA | 2 | 181 |
# of filed Patents : 2 Total Citations : 181 | |||
Fletcher, Thomas G | Waterdown, CA | 5 | 215 |
# of filed Patents : 5 Total Citations : 215 | |||
Hawke, Robert E | Burlington, CA | 3 | 197 |
# of filed Patents : 3 Total Citations : 197 | |||
McNeil, Lynn | Waterdown, CA | 1 | 181 |
# of filed Patents : 1 Total Citations : 181 | |||
Patel, Atin J | Mississauga, CA | 11 | 255 |
# of filed Patents : 11 Total Citations : 255 |
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Patent Citation Ranking
- 181 Citation Count
- H01L Class
- 98.23 % this patent is cited more than
- 25 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text

Legal Events
Date | Code | Event | Description |
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Dec 29, 2014 | STCH | INFORMATION ON STATUS: PATENT DISCONTINUATION | free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
Dec 03, 2014 | FP | LAPSED DUE TO FAILURE TO PAY MAINTENANCE FEE | Effective Date: Dec 03, 2014 |
Dec 03, 2014 | LAPS | LAPSE FOR FAILURE TO PAY MAINTENANCE FEES | |
Jul 11, 2014 | REMI | MAINTENANCE FEE REMINDER MAILED | |
Jun 03, 2010 | FPAY | FEE PAYMENT | year of fee payment: 8 |
Jun 05, 2006 | FPAY | FEE PAYMENT | year of fee payment: 4 |
Dec 03, 2002 | I | Issuance | |
Apr 19, 2000 | F | Filing | |
Mar 22, 2000 | AS | ASSIGNMENT | free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MORRIS, DAVID PAUL;DANG, NGUYEN THAI;REEL/FRAME:010805/0936 Owner name: PRC-DESOTO INTERNATIONAL, INC., CALIFORNIA Effective Date: Mar 22, 2000 |
Oct 20, 1997 | PD | Priority Date |

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