Semiconductor device
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United States of America Patent
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Oct 10, 2000
Issued Date -
N/A
app pub date -
Apr 13, 1999
filing date -
Sep 20, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
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