Method and apparatus for partial word read through ECC block
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United States of America Patent
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Sep 26, 2000
Grant Date -
N/A
app pub date -
Apr 21, 1998
filing date -
Apr 21, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
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