Circuit and method for protocol header decoding and packet routing
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United States of America Patent
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Sep 19, 2000
Grant Date -
N/A
app pub date -
Aug 7, 1997
filing date -
Aug 7, 1997
priority date (Note) -
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Abstract
A digital delay line, comprising adjustable digital delay elements coupled in series, receives and buffers a packet bit stream. The outputs of selected adjustable digital delay elements are tapped for determining in parallel the destination address bits of the packet. The packet is routed at the end of the digital delay line to the destination indicated by the destination address bits.
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