Memory device having a crested tunnel barrier
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United States of America Patent
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Sep 19, 2000
Grant Date -
N/A
app pub date -
Oct 10, 1997
filing date -
Oct 10, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A nonvolatile, high-speed, bit-addressable memory device is disclosed. A tunnel barrier layer is disposed between a charge supply medium and a charge storage medium, with the tunnel barrier layer having a crested energy profile with a maximum half-way between the charge storage layer and the charge supply layer.
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