Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
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United States of America Patent
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Aug 22, 2000
Grant Date -
N/A
app pub date -
Nov 3, 1998
filing date -
Aug 18, 1998
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Abstract
Described herein is a method of manufacturing a semiconductor device according to the invention of the present application. According to the method, protruded electrodes are formed on a plurality of chip areas of a wafer having the plurality of chip areas on the surface thereof. Grooves are defined in boundary regions of the plurality of chip areas. Thereafter, the surface of the wafer with the grooves defined therein is covered with a resin. The back of the wafer is polished to expose the grooves from the back thereof. Next, the wafer is divided into pieces at the exposed groove portions. Since the grooves are bare from the back of the wafer in this way, the positions where the wafer is divided into the pieces, can be recognized with ease and reliability.
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