Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas
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United States of America Patent
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Aug 15, 2000
Grant Date -
N/A
app pub date -
May 1, 1997
filing date -
May 1, 1997
priority date (Note) -
Expired
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Abstract
FET devices are manufactured using STI on a semiconductor substrate coated with a pad from which are formed raised active silicon device areas and dummy active silicon mesas capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide layer is deposited on the device with conformal projections above the mesas. Then a polysilicon film on the blanket silicon oxide layer is deposited with conformal projections above the mesas. The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer is exposed over the pad structures. Selective RIE partial etching of the conformal silicon oxide layer over the mesas is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride as an etch stop.
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