Passivation of copper interconnect surfaces with a passivating metal layer

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United States of America Patent

PATENT NO 6100195
SERIAL NO

09222275

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Abstract

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An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL UNIVERSITY OF SINGAPORE21 LOWER KENT RIDGE ROAD SINGAPORE 119077
CHARTERED SEMICONDUCTOR MANUFACTURING LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406
INSTITUTE OF MICROELECTRONICSSINGAPORE 117685
NANYANG TECHNOLOGICAL UNIVERSITY OF SINGAPORENANYANG AVENUE SINGAPORE 639798

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Lap San Francisco, CA 159 4868
Ip, Flora S Singapore, SG 2 128
Loh, Wye Boon Johor, MY 7 212
Tee, Kheng Chok Selangor, MY 24 524
Yap, Kuan Pei Selangor, MY 7 129

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