Method for manufacturing a high performance transistor with self-aligned dopant profile
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United States of America Patent
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Aug 8, 2000
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N/A
app pub date -
Apr 16, 1998
filing date -
Apr 16, 1998
priority date (Note) -
Expired
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Abstract
A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source/drain regions of the substrate. The source-drain mask is removed and an oxidation layer is grown, where portions of the oxidation layer formed from doped regions of the substrate have heights that are greater than heights of portions of the oxidation layer formed from un-doped regions of the substrate, thereby forming a gate mask. The doped portions of the substrate are self-aligned with gate regions of the substrate. The gate regions are doped, and gate electrodes are formed. The gate mask is removed to expose source/drain regions of the substrate for further fabrication.
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