System to fix post-layout timing and design rules violations
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United States of America Patent
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Aug 8, 2000
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N/A
app pub date -
Dec 6, 1996
filing date -
Dec 6, 1996
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Abstract
A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.
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