Importance

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Abstract

A circuit for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels. If adjustments to bit loadings are required to achieve a particular initial target rate, the circuit first adjusts those sub-channels which will have the least effect on the overall system performance margin, so that compliance with system requirements is better achieved. In addition, an 'iteration criteria' count can be incorporated to ensure that the initialization of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

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First Claim