High drive CMOS output buffer with fast and slow speed controls
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United States of America Patent
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-
Jul 25, 2000
Grant Date -
N/A
app pub date -
May 12, 1997
filing date -
May 12, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.
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