Data processor and data processing system having two translation lookaside buffers
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United States of America Patent
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Jul 18, 2000
Grant Date -
N/A
app pub date -
Oct 15, 1997
filing date -
Oct 16, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.
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