Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM)
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United States of America Patent
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Jul 4, 2000
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N/A
app pub date -
Mar 10, 1998
filing date -
Mar 10, 1998
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Abstract
An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation within the AMPIC memories themselves to guarantee that only valid requested data is returned from them, or properly marked invalid data. A modified technique for identifying bad data that has been read out of AMPIC memory devices in the system.
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