Cache system configurable for serial or parallel access depending on hit rate
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United States of America Patent
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Jun 27, 2000
Grant Date -
N/A
app pub date -
Jun 11, 1998
filing date -
Aug 21, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processing system having a CPU (central processing unit), a system bus and a main memory connected to the system bus, comprises a cache memory connected to the system bus for storing a predetermined part of data stored at the main memory, a first path unit for coupling the CPU with the cache memory, a second path unit for connecting the CPU to the system bus, and controller for enabling one of the first and the second path units. In the data processing system, the main memory is accessed only if a cache miss occurs while the first path unit is enabled, and the main memory and the cache memory are accessed simultaneously while the second path unit is enabled.
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