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Abstract

The present invention discloses a novel electronic package. This semiconductor packaging assembly is for supporting and containing an integrated circuit (IC) chip. The IC chip is supported on a single core double-layer substrate as a flip chip which is solder-bumped with low melting point solder, e.g., a 63 wt % Sn-37 wt % Pb eutectic solder. The flip chip is supported on a single core double-sided FR-4/5 or BT substrate provided with via holes to form via connections interconnecting the solder bumps to a land grid array disposed on the bottom surface of the substrate. The substrate is then surface mounted and soldered onto a printed circuit board which again is provided with low temperature 63 wt % Sn-37 wt % Pb eutectic solder paste for securely attaching the LGA CSP. Simplified processes are employed to assemble the electronic package with high yield processing steps, which can be conveniently carried out. CSP package with high reliability and improved performance characteristics can be achieved with a reduced production cost. This invention further discloses a tape-substrate provided for interposing between a semiconductor chip and a printed circuit board (PCB). The tape substrate includes a bottom insulation layer. The tape substrate further includes a plurality of conductive pads disposed on top of the bottom insulation layer for electrical connection to the semiconductor chip. The tape substrate further includes a plurality of PCB contact-openings opened in the insulation layer and a plurality of PCB contact-pads, each covering one of the PCB contact-openings for electrical connection to circuit on the PCB. The tape substrate further includes a plurality of connection means for interconnecting the conductive pads to the PCB contact-pads.

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First Claim