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Abstract

A high-speed processor system having a bus arbitration mechanism constructed on a single semiconductor chip. The processor system comprises at least one bus master, a plurality of buses and a plurality of bus slaves. Each bus comprises an independent address bus, an independent data bus and individual data transfer capability. Every bus master comprises a plurality of independent bus interfaces each connected to one of the buses. Each bus slave is connected to a bus that has corresponding data transfer capability. For a system having more than two bus masters, the system further comprises a plurality of bus arbitrators for arbitrating the access of each bus independently. The bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus. The bus arbitrator comprises a plurality of priority order information storage devices for storing priority order information for all the bus masters connected to the bus. At every bus cycle, one set of priority order information is selected continuously and cyclically. When more than one bus master requests the bus access at the same time, the bus arbitrator determines which bus master may access the bus according to selected priority order information.

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First Claim