Integrated circuit including vertical transistors with spacer gates having selected gate widths
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United States of America Patent
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May 30, 2000
Grant Date -
N/A
app pub date -
Mar 4, 1997
filing date -
Mar 4, 1997
priority date (Note) -
Expired
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Abstract
Improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. A method of fabricating an integrated circuit includes forming a plurality of doped layers in a series of depths in a substrate wafer, and etching a trench in the substrate wafer. The trench extends through the doped layers at a plurality of depths and is bounded by vertical sidewalls and a planar horizontal floor. The method further includes forming a conductive sidewall spacer adjacent to the vertical sidewalls of the trench.
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