Memory integrated circuit supporting maskable block write operation and arbitrary redundant column repair
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United States of America Patent
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May 9, 2000
Grant Date -
N/A
app pub date -
Jul 14, 1998
filing date -
Jul 14, 1998
priority date (Note) -
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Abstract
A memory circuit column decoder is provided with an array of fuses that can be selectively blown to indicate a fuse address of a defective column of a memory array to be substituted by a redundant column. The memory circuit column decoder also includes a decoder that receives a mask that selectively masks out certain columns of a group of columns from being written during a block write operation, and the fuse address from the array of fuses. The decoder generates a signal for disabling the redundant column during a block write operation when the mask masks out the defective column.
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