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Abstract

Methods of forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells therein includes the steps of forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and then forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is then formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is then formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to thereby define a plurality of vertical IGBT cells. The array of anode regions is also spaced between adjacent collector regions to define a plurality of freewheeling diode cells which are connected in antiparallel relative to the IGBT cells. The insulated gate electrode is also preferably patterned to extend between adjacent collector and anode regions so that in the event parasitic thyristor latch-up of the IGBT cells occurs, the collector regions can be electrically connected to the anode regions. This electrical connection reduces the effective resistance of the collector regions and reduces the likelihood that the P-N junction formed at the collector-source junction will become or remain forward biased.

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