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Abstract

A digital data storage arrangement includes a storage register for storing a data word having a predetermined number of data bits along with an error correction code, a data input circuit and a data output circuit. The data input circuit receives an input data word having a number of data bits with at most a selected larger number of data bits than can be stored in said storage register, and generates an error correction code value in response to all of the data bits of said input data word. The data input circuit couples the data word, comprising the predetermined number of data bits of the input data word, along with the error correction code value for storage in the storage register. Thus, if the number of bits of the input data word exceeds the predetermined number of bits that can be stored in the storage register, the storage register only stores the predetermined number of data bits, not all of the bits of the input data word. The data output circuit retrieves the data word and the error correction code from storage register and using the error correction code, generates an output data word which corresponding to the input data word provided by the data input circuit. In particular, the error correction code permits the data output circuit to generate an output data word that includes, in addition to the portion of the input data word that was stored in the storage register, the missing bits that were not stored in the storage register.

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