DMOS transistor protected against "snap-back"

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United States of America Patent

PATENT NO 6043532
SERIAL NO

08965840

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Abstract

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The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the 'snap-back' phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

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Patent Owner(s)

Patent OwnerAddress
SGS-THOMSON MICROELECTRONICS S R LITALY AGELITE BRIANZA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Depetro, Riccardo Domodossola, IT 30 188
Palmieri, Michele Settimo Milanese, IT 25 251

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