Semiconductor memory device having selection circuit for arbitrarily setting a word line to selected state at high speed in test mode
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United States of America Patent
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Mar 7, 2000
Grant Date -
N/A
app pub date -
Mar 6, 1998
filing date -
Sep 8, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.
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