Method of fabricating dual voltage MOS transistors
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United States of America Patent
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-
Mar 7, 2000
Grant Date -
N/A
app pub date -
Jun 30, 1998
filing date -
Apr 13, 1998
priority date (Note) -
Expired
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Abstract
A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.
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