Electrically isolated interconnects and conductive layers in semiconductor device manufacturing
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United States of America Patent
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Jan 4, 2000
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N/A
app pub date -
Oct 15, 1996
filing date -
Oct 15, 1996
priority date (Note) -
Expired
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Abstract
A method for fabricating microelectronic deices in which an interconnect layer is electrically isolated from large protuberances that project from a lower conductive layer to a desired endpoint of a chemical-mechanical planarization process. The lower conductive layer is covered with an insulating material to form an insulator layer that generally follows the contour of the lower conductive layer and any large protuberances. A highly conductive interconnect material is then deposited over the insulator layer to form an interconnect layer that generally follows the contour of the insulator layer. The interconnect layer may be deposited directly on the insulator layer, or it may be deposited on an intermediate layer between the interconnect layer and the insulator layer. After the upper conductive layer is deposited, the insulator layer and the upper conductive layer are planarized with a chemical-mechanical planarization process to a desired endpoint.
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