Parametric test system and method
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United States of America Patent
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Dec 28, 1999
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N/A
app pub date -
Mar 2, 1998
filing date -
Mar 2, 1998
priority date (Note) -
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Abstract
A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.
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