Template used for polishing a semiconductor wafer
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United States of America Patent
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-
Dec 14, 1999
Grant Date -
N/A
app pub date -
May 30, 1997
filing date -
May 31, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A backing pad 7 is secured on the bottom of a ceramic plate 6. A template 1 is secured on the bottom of the backing pad 7. The thickness of the template 1 successively diminishes from the inner periphery wall 12 of the central accommodation opening for restraining the semiconductor wafer, toward the outer periphery wall 13 of the template 1, so that the bottom of the template 1 is inclined and the cross section of the template 1 is tapered.
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