Method for making three dimensional circuit integration
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United States of America Patent
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Dec 7, 1999
Grant Date -
N/A
app pub date -
Nov 12, 1997
filing date -
Nov 12, 1997
priority date (Note) -
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Abstract
The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.
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