Level converting circuit having a high switching speed
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United States of America Patent
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Nov 30, 1999
Grant Date -
N/A
app pub date -
Sep 10, 1998
filing date -
Sep 10, 1997
priority date (Note) -
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Abstract
The level converting circuit has first and second transistors of a first conductivity type. The control terminals of the transistors are connected to a first supply potential via the load path of the respective other transistor. A load path of a third transistor of a second conductivity type is connected between the control terminal of the first transistor and a reference-ground potential. The control terminal of the third transistor is coupled to the input of the level converting circuit. A node between the second and third transistors forms the output of the circuit. A fourth transistor of the second conductivity type has a load path connected between the control terminal of the second transistor and the control terminal of the third transistor. A capacitance is connected between the control terminals of third and fourth transistors. A limiter circuit is connected upstream of the control terminal of the fourth transistor.
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